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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13606-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90620A Series
MB90622A/623A/P623A
s DESCRIPTION
The MB90620A series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing, proving to be suitable for various industrial machines, camera and video devices, OA equipment, and for process control. The CPU used in this series is the F2MC*-16L. The instruction set for the F2MC-16L CPU core is designed to be optimized for controller applications while inheriting the AT architecture of the F2MC-16/16H series, allowing a wide range of control tasks to be processed efficiently at high speed. The peripheral resources integrated in the MB90620A series include: the UART (clock asynchronous/ synchronous transfer) x 1 channel, the extended serial I/O interface x 1 channel, the A/D converter (8/10-bit precision) x 4 channels, the 16-bit PPG timer (PWM/single-shot function) x 2 channels, the 16-bit reload timer x 3 channels, the 16-bit free-run timer (built-in compare register: 2 channels) x 2 channels, the external interrupt x 8 channels, the watch timer x 1 channel, LCD controller/driver 32 segments x 4 commons. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
F2MC-16L CPU
* Minimum execution time: 83.33 ns (at machine clock frequency of 12 MHz) * Dual-clock control systems * PLL clock control
(Continued)
s PACKAGE
100-pin Plastic LQFP
(FPT-100P-M05)
MB90620A Series
(Continued) * Instruction set optimized for controller applications Variety of data types: bit, byte, word, long-word Expanded addressing modes: 23 types High coding efficiency Improvement of high-precision arithmetic operations through use of 32-bit accumulator * Instruction set supports high-level language (C language) and multitasking Inclusion of system stack pointer Enhanced pointer-indirect instructions Barrel shift instruction * Improved execution speed: 4-byte instruction queue * 8-level, 32-factor powerful interrupt service functions * Automatic transfer function independent of CPU (EI2OS) * General-purpose ports: max. 59 channels * 18-bit timebase timer/15-bit watch timer * Watchdog timer function * CPU intermittent operation function * Various standby modes
Peripheral blocks
* ROM:32 Kbytes (MB90622A) 48 Kbytes (MB90623A) * One-time PROM: 48 Kbytes (MB90P623A) * RAM: 1.64 Kbytes (MB90622A) 2 Kbytes (MB90623A/P623A) * General-purpose ports: max. 59 channels * Dual-clock control system * PLL clock multiplication control system * UART: 1 channel Can be used for either asynchronous transfer or synchronous transfer with clock * Extended serial I/O interface: 1 channel Can be used for 8-bit synchronous transfer * A/D converter (8/10-bit resolution): 4 channels * PPG (Programable pulse generator): 2 channels * 16-bit reload timer: 3 channels * 16-bit free-run timer: 2 channels With compare register 2 channels * LCD controller/driver 32 segments, 4 commons * External interrupts: 8 channels * 18-bit timebase timer * 15-bit watch timer * Watchdog timer function * CPU intermittent operation function * Standby mode Watch mode Sleep mode Stop mode
2
MB90620A Series
s PRODUCT LINEUP
Part number Parameter
MB90622A
MB90623A
MB90P623A One-time model 48 Kbytes 2 Kbytes
Classification ROM size RAM size CPU functions
Mass production products (Mask ROM products) 32 Kbytes 1.64 Kbytes 48 Kbytes 2 Kbytes
Number of instructions: 340 Instruction bit length: 8 or 16 bits Instruction length: 1 to 7 bytes Data bit length: 1, 4, 8, 16, or 32 bits Minimum execution time: 83.33 ns at 12 MHz (internal) Dual-clock system of main clock and sub clock Max. 59 channels I/O ports (CMOS): 17 I/O ports (CMOS) with pull-up resistor available: 24 I/O ports (open drain): 18 Number of channels: 1 Clock synchronous communication (1202 to 9615 bps, full-duplex double buffering) Clock asynchronous communication (62.5 K to 1 M bps, full-duplex double buffering) Supports multiprocessor mode Number of channels: 1 Internal or external clock mode Clock synchronous transfer (62.5 kHz to 1 MHz, "LSB first" or "MSB first" transfer) Resolution: 10 or 8 bits, Number of input channels: 4 Single-conversion mode (conversion for a specified input channel) Scan conversion mode (continuous conversion for specified consecutive channels) Continuous conversion mode (repeated conversion for a specified channel) Stop conversion mode (periodical conversion) Number of channels: 3 16-bit reload timer operation (operation clock: SUB/2, /23, /25, external) Number of channels: 2 16-bit up-counter (four types of count clocks) 2 channels on each timer of the compare register (compare matching interrupt available) Number of channels: 2 PWM function, single-shot function With external trigger function Common output: 4 channels, Segment output: 32 channels Direct driving of the LCD module 16 bytes of data memory for display Operation clock source (main clock/sub clock selective) Stop mode, sleep mode, and watch mode Main clock multiplication (x1, x2, x3 and x4) FPT-100P-M05
Oscillation circuit Ports
UART
Serial
A/D converter
Timer Free-run timer
PPG timer
LCD controller /driver
Standby modes PLL functions Package
3
MB90620A Series
s PIN ASSIGNMENT
(Top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06/INT6 P05/INT5 P04/INT4 P03/INT3 P02/INT2 P01/INT1 P00/INT0 V CC X1 X0 V SS X0A X1A SEG31/P77
4
V2 V3 COM0 COM1 COM2 COM3 AV CC AVRH AVRL AV SS P50/AN0 P51/AN1 P52/AN2 P53/AN3 V SS SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 MD0 MD1 MD2 SEG06
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P22 P23 P24/SIN0 P25/SOT0 P26/SCK0 P27/CKOT P30/SIN1 P31/SOT1 V SS P32/SCK1 P33 P34 P35 P36 P37/TRG/ATG P40/PPG0 P41/PPG1 P42/INT7/TIO0 P43/TIO1 P44/TIO2 V CC P45 P46 V0 V1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RST P76/SEG30 P75/SEG29 P74/SEG28 P73/SEG27 P72/SEG26 P71/SEG25 P70/SEG24 P67/SEG23 P66/SEG22 P65/SEG21 P64/SEG20 P63/SEG19 P62/SEG18 P61/SEG17 P60/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG07
(FPT-100P-M05)
MB90620A Series
s PIN DESCRIPTION
Pin no. 77 78 79 80 81 82 83 to 89 Pin name X1A X0A VSS X0 X1 VCC P00 to P06 Circuit type A (Oscillation) A (Oscillation) M (CMOS/H) Function Crystal oscillator pins (32 kHz)
Power supply Digital circuit power supply (GND) pin Crystal/FAR oscillator pins (4 MHz)
Power supply Digital circuit power supply pin General-purpose I/O ports At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. External interrupt request input pins When external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. G (CMOS) G (CMOS) G (CMOS) F (CMOS/H) General-purpose I/O port At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. General-purpose I/O ports At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. General-purpose I/O ports At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. General-purpose I/O port At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. UART serial data input pin During UART input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. G (CMOS) General-purpose I/O port At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. UART serial data output pin This function is available when the UART serial data output is enabled. F (CMOS/H) General-purpose I/O port At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. UART serial data I/O pin This function is available when the UART clock output is enabled. During UART input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately.
INT0 to INT6
90
P07
91 to 98
P10 to P17
99, 100 1, 2 3
P20 to P23
P24
SIN0
4
P25
SOT0
5
P26
SCK0
(Continued)
5
MB90620A Series
Pin no. 6
Pin name P27
Circuit type G (CMOS)
Function General-purpose I/O port At this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. Clock output pin This function is available when clock output is enabled.
CKOT 7 P30 SIN1 E (CMOS/H)
General-purpose I/O port I/O extended serial data input pin This pin, as required, is used for input during input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port I/O extended serial data output pin This function is available when serial data data output is enabled. General-purpose I/O port I/O extended serial clock I/O pins This function is available when clock input is enabled. This pin, as required, is used for input during input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O ports General-purpose I/O port PPG0 and PPG1 external trigger input pin A/D converter trigger input pin During A/D converter input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately.
8
P31 SOT1
D (CMOS)
9 10
VSS P32 SCK1
Power supply Digital circuit power supply (GND) pin E (CMOS/H)
11 to 14 15
P33 to P36 P37 TRG ATG
D (CMOS) E (CMOS/H)
16
P40 PPG0
D (CMOS)
General-purpose I/O port This function is available when PPG timer 0 output is disabled. PPG timer 0 output pin This function is available when the PPG timer 0 waveform output is enabled.
17
P41 PPG1
D (CMOS)
General-purpose I/O port This function is available when PPG timer 1 output is disabled. PPG timer 1 output pin This function is available when the PPG timer 1 waveform output is enabled.
(Continued)
6
MB90620A Series
Pin no. 18
Pin name P42
Circuit type L (CMOS/H)
Function General-purpose I/O port This function is available when the timer output from timer 0 is disabled. External interrupt request input pin When external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. Timer input pin The data on this pin is used as event count signal for timer 0. Timer output pin This function is available when the timer output from timer 0 is enabled.
INT7
TIO0
19
P43
E (CMOS/H)
General-purpose I/O port This function is available when the timer output from timer 1 is disabled. Timer input pin The data on this pin is used as event count signal for timer 1. Timer output pin This function is available when the timer output from timer 1 is enabled.
TIO1
20
P44
E (CMOS/H)
General-purpose I/O port This function is available when the timer output from timer 2 is disabled. Timer input pin The data on this pin is used as event count signal for timer 2. Timer output pin This function is available when the timer output from timer 2 is enabled.
TIO2
21 22, 23 24 to 27 28 to 31 32
VCC P45, P46 V0 to V3 COM0 to COM3 AVCC
Power supply Digital circuit power supply pin H (CMOS) K Open-drain I/O ports
Power supply LCDC reference power supply pins LCDC common pins
Power supply Analog circuit power supply pin This power supply must only be turned on or off when electric potential of AVCC or greater is applied to VCC. Power supply Analog circuit reference voltage input pin This pin must only be turned on or off when electric potential of AVRH or greater is applied to AVCC. Power supply Analog circuit reference voltage input pin Power supply Analog circuit power supply (GND) pin
33
AVRH
34 35
AVRL AVSS
(Continued)
7
MB90620A Series
(Continued)
Pin no. 36 to 39 Pin name P50 to P53 Circuit type I (AD) Function General-purpose I/O ports This function is available when "port" is specified in the analog input enable register. A/D converter analog input pins This function is available when the analog input enable register specification is "AD." Power supply Digital circuit power supply (GND) pin K C (CMOS) K J LCDC segment-only pins Operating mode selection input pins Connect directly to VCC or VSS. LCDC segment-only pins Open-drain I/O ports This is available when enabled by the LCR2. LCDC segment pins J Open-drain I/O ports This is available when enabled by the LCR2. LCDC segment pins B (CMOS/H) J External reset request input pin Open-drain I/O port This is available when enabled by the LCR2. LCDC segment pin
AN0 to AN3
40 41 to 46 47 to 49 50 to 59 60 to 67
VSS SEG00 to SEG05 MD0 to MD2 SEG06 to SEG15 P60 to P67 SEG16 to SEG23
68 to 74
P70 to P76 SEG24 to SEG30
75 76
RST P77 SEG31
8
MB90620A Series
s I/O CIRCUIT TYPE
Type A
X1 (A)
Circuit
Remarks * Oscillation feedback resistor: Approximately 1 M
X0 (A)
Standby control signal
B
* Hysteresis input with pull-up resistor
C
* CMOS input port
D
V CC Digital output
* CMOS level input/output
Digital output V SS Diffused resistor CMOS Standby control signal
E
* CMOS level output * Hysteresis input
Standby control signal
(Continued)
9
MB90620A Series
Type F
Circuit
Remarks * With input pull-up resistor control * CMOS level output * Hysteresis input
Pull-up control
Standby control signal
G
Pull-up control
* With input pull-up resistor control * CMOS level input/output
CMOS Standby control signal
H
* Open-drain type input/output
CMOS Standby control signal
I
* CMOS level input/output * Analog input
Analog input
CMOS Standby control signal
(Continued)
10
MB90620A Series
(Continued)
Type J Circuit Remarks * Open-drain type output * CMOS level input * Combined with the LCD output
LCD output
LCD output
CMOS Standby control signal
K
* LCD output pin
LCD output
LCD output
L
* CMOS level output * Hysteresis input
M
Pull-up controller
* With input pull-up resistor control * CMOS level output * Hysteresis input
11
MB90620A Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to the input and output pins other than medium- and high voltage pins or if higher than the voltage is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistors.
3. External Reset Input
To reset the internal circuit by the Low-level input to the RST pin, the Low-level input to the RST pin must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
4. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
5. Precautions when Using an External Clock
When an external clock is used, drive X0 pin. * Using of External Clock
X0, (X0A) MB90620A X1, (X1A)
6. Sequence for Applying A/D Converter Power Supply and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying the A/D converter power supply (AVCC, AVRH, and AVRL) and the analog inputs (AN0 to AN15). In addition, when the power is turned off, turn off the A/D converter power supply (AVCC, AVRH, and AVRL) and the analog inputs (AN0 to AN15) first, and then turn off the digital power supply (AVCC). Whether applying or cutting off the power, be certain that AVRH does not exceed AVCC.
7. Program Mode
In the MB90P623, all of the bits (48 K x 8 bits) are set to "1" when the IC is shipped from Fujitsu and after erasure. To input data, program the IC by selectively setting the desired bits to "0". Bits cannot be set to "1" electrically.
12
MB90620A Series
8. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM width microcontroller program.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
9. Programming Yield
All bit cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
13
MB90620A Series
s PROGRAMMING TO THE EPROM ON THE MB90P623A
In EPROM mode, the MB90P623 EPROM functions equivalent to the MBM27C1000. This allows the PROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter.
1. EPROM Mode Pin Assignments * MBM27C1000 compatible pins
MBM27C1000 Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name VPP OE* A15 A12 A07 A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 GND* MB90P623A Pin no. 49 10 98 95 6 5 4 3 2 1 100 99 83 84 85 -- Pin name MD2 (VPP) P32 P17 P14 P27 P26 P25 P24 P23 P22 P21 P20 P00 P01 P02 -- MBM27C1000 Pin no. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin name VCC PGM N.C. A14 A13 A08 A09 A11 A16 A10 CE A07 D06 D05 D04 D03 MB90P623A Pin no. -- 11 -- 97 96 91 92 94 7 93 8 90 89 88 87 86 Pin name -- P33 -- P16 P15 P10 P11 P13 P30 P12 P31 P07 P06 P05 P04 P03
* : Connect a capacitance of 20 pF across OE (pin no.2) and GND (pin no.16) pins of the MBM27C1000.
* Power supply, GND connection pins
Classification Power supply Pin no. 21 82 9 34 35 40 75 79 12 13 14 Pin name VCC VCC VSS AVRL AVSS VSS RST VSS P34 P35 P36
GND
14
MB90620A Series
* Non-MBM27C1000 compatible pins
Pin no. 47 48 80 78 81 77 28 to 31 41 to 46 50 to 59 15 16 to 20 22 23 24 to 27 32 33 36 to 39 60 to 74 76 Pin name MD0 MD1 X0 X0A X1 X1A COM0 to COM3 SEG00 to SEG05 SEG06 to SEG15 P37 P40 to P44 P45 P46 V0 to V3 AVCC AVRH P50 to P53 P60 to p76 P77 Treatment Connect a pull-up resistor of 4.7 k
OPEN
Connect a pull-up resistor of about 1 M to each pin.
2. EPROM Programmer Socket Adapter
Part no. MB90P623APFV Package SQFP-100 Compatible socket adapter Sun Hayato Co., Ltd. ROM-100SQF-32DP-16L
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106
15
MB90620A Series
3. Programming Procedure
(1) Set the EPROM programmer to the MBM27C1000. (2) Load the program data into the EPROM programmer at 14000H to 1FFFFH. The ROM addresses from FF4000H to FFFFFFH in operating mode of MB90P623A series correspond to 14000H to 1FFFFH in EPROM mode.
Operating mode FFFFFFH EPROM FF4000H 14000H 1FFFF H
EPROM mode
EPROM
(3) Insert the MB90P623A in the socket adapter, and mount the socket adapter on the EPROM programmer. Pay attention to the orientation of the device and of the socket adapter when doing so. (4) Activate the programming. (5) If programming cannot be performed successfully, connect a 0.1 F or similar capacitor between VCC and GND and between VPP and GND. Note: Because the mask ROM products (MB90623A) do not have an EPROM mode, they cannot read data from the EPROM programmer.
16
MB90620A Series
s BLOCK DIAGRAM
X0, X1 RST X0A, X1A MD0 to MD2
6
Clock controller
CPU F2MC-16L Interrupt controller
RAM 3 ROM Timer x 3 TIO0 to TIO2
UART
F2MC-16L bus
SIN0 SOT0 SCK0
Free-run timer x 2 + Compare register 2
CKOT
Communication prescaler
SIN1 SOT1 SCK1
Extended serial I/O interface
PPG x 2 8 External interrupt
PPG0, PPG1 TRG
INT0 to INT7
AV cc 2 AVRH, AVRL AV ss ATG 4 AN0 to AN3
40 A/D converter LCD controller/driver SEG00 to SEG31 V0 to V3 COM0 to COM3
I/O ports 8 P00 to P07 8 P10 to P17 8 P20 to P27 8 P30 to P37 7 P40 to P46 4 P50 to P53 8 P60 to P67 8 P70 to P77
* P00 to P27 (24 channels): Input pull-up resistor setting enable pins * P45, P46, P60 to P77 (18 channels): Open-drain pins
17
MB90620A Series
s MEMORY MAP
FFFFFFH ROM area Address#1
FF0000H
010000H ROM area (FF bank image) Address#2
: Internal access 004000H 002000H Address#3 RAM 000100H 0000C0H Peripherals 000000H Product MB90622A MB90623A MB90P623A Address #1 FF8000H FF4000H FF4000H Address #2 008000H 004000H 004000H Register : No access
Address #3 000780H 000900H 000900H
Note: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit effective use of the C compiler's small model. Because the lower 16 bits of bank FF address and the lower 16 bits of bank 00 are the same, it is possible to reference tables in ROM without declaring the "far" specification in the pointer.
18
MB90620A Series
s I/O MAP
Address Register Register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 Vacancy* DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 Vacancy* RDR0 RDR1 RDR2 ADER CKOT Vacancy* SMR SCR SIDR/ SODR SSR SMCS SDR R/W R/W R/W R/W R/W R/W Extended serial I/O interface UART 00000000 00000100 XXXXXXXX 0001--00 ---00000 00000010 XXXXXXXX R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 A/D
Clock output (CKOT)
Access R/W R/W R/W R/W R/W R/W R/W R/W
Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX - XXXXXXX - - - - XXXX XXXXXXXX - XXXXXXX
000000H Port 0 data register 000001H Port 1 data register 000002H Port 2 data register 000003H Port 3 data register 000004H Port 4 data register 000005H Port 5 data register 000006H Port 6 data register 000007H Port 7 data register 000008H to 0FH 000010H Port 0 direction register 000011H Port 1 direction register 000012H Port 2 direction register 000013H Port 3 direction register 000014H Port 4 direction register 000015H Port 5 direction register 000016H Port 6 direction register 000017H Port 7 direction register 000018H to 19H 00001AH Port 0 pull-up resistor setting register 00001BH Port 1 pull-up resistor setting register 00001CH Port 2 pull-up resistor setting register 00001DH Analog input enable register 00001EH Clock output enable register 00001FH 000020H Serial mode register 000021H Serial control register 000022H Serial input register/ Serial output register
R/W R/W R/W R/W R/W R/W R/W R/W
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7
00000000 00000000 00000000 00000000 -0000000 ----0000 00000000 00000000
00000000 00000000 00000000 ----1111 ----0000
000023H Serial status register 000024H 000025H Serial mode control status register
000026H Serial data register
(Continued)
19
MB90620A Series
Address 000027H
Register Communication prescaler control register
Register name CDCR ENIR EIRR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PCSR0 PDUT0 PCNL0 PCNH0 Vacancy*
Access R/W R/W R/W R/W R/W
Resource name
Initial value
UART, I/O, serial 0 - - - 1 1 1 1 00000000 DTP/external interrupt 00000000 00000000 00000000 00000000 8/10-bit A/D converter 00000000 XXXXXXXX 0 0 0 0 0 0 XX XXXXXXXX XXXXXXXX 16-bit PPG timer 0 XXXXXXXX XXXXXXXX 00000000 0000000-
000028H DTP/Interrupt enable register 000029H DTP/Interrupt source register 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H to 37H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH, 3FH 000040H 000041H 000042H 000043H 000044H 000045H Timer control status register 16-bit timer register 16-bit reload register PPG1 cycle setting register PPG1 duty factor setting register PPG1 control status register Request level setting register A/D control status register A/D data register PPG0 cycle setting register PPG0 duty factor setting register PPG0 control status register
R/W W W R/W
PCSR1 PDUT1 PCNL1 PCNH1 Vacancy* TMCSR0 TMR0 TMRLR0
W W R/W 16-bit PPG timer 1
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 0000000-
R/W R/W R/W 16-bit reload timer 0
00000000 ----0000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
20
MB90620A Series
Address 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH to 4FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H
Register Timer control status register 1 16-bit timer register 1 16-bit reload register 1
Register name TMCSR1 TMR1 TMRLR1 Vacancy*
Access R/W R/W R/W
Resource name
Initial value 00000000 ----0000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit reload timer 1
Timer control status register 2 16-bit timer register 2 16-bit reload register 2 Timer data register 0
TMCSR2 TMR2 TMRLR2 TCDT0 TCS0 CCS0 TCR00 TCR01 Vacancy*
R/W R/W R/W R R/W R/W R/W R/W Compare register block 16-bit reload timer 2
00000000 ----0000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 16-bit free-run timer 0 00000000 00000000 0000--00 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000058H Timer control status register 0 000059H Compare control status register 0 00005AH 00005BH 00005CH 00005DH 00005EH, 5FH 000060H 000061H Timer data register 1 Timer 0 compare register 0 Timer 0 compare register 1
TCDT1 TCS1 CCS1 TCR10 TCR11
R R/W R/W R/W R/W
00000000 16-bit free-run timer 1 00000000 00000000 0000--00 XXXXXXXX Compare register block XXXXXXXX XXXXXXXX XXXXXXXX
000062H Timer control status register 1 000063H Compare control status register 1 000064H 000065H 000066H 000067H Timer 1 compare register 0 Timer 1 compare register 1
(Continued)
21
MB90620A Series
Address 000068H to 6FH
Register
Register name Vacancy* VRAM LCR0 LCR1 Vacancy*
Access
Resource name
Initial value
000070H LCD display data RAM to 7FH 000080H LCDC control register 0 000081H LCDC control register 1 000082H to 8FH 000090H to 9EH 00009FH 0000A0H Delayed interrupt source generation/ release register Low-power consumption mode control register
R/W LCD controller/ driver R/W
XXXXXXXX XXXXXXXX 00010000 0--00000
System reserved area* DIRR LPMCR CKSCR Vacancy* WDTC TBTC WTC Vacancy* ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 R/W R/W R/W Watchdog timer Timebase timer Watch timer XXXXXXXX 1--00000 1 X- 0 0 0 0 0 R/W R/W R/W
Delayed interrupt generation module
-------0 00011000 11111100
0000A1H Clock selection register 0000A2H to A7H 0000A8H Watchdog timer control register 0000A9H Timebase timer control register 0000AAH Watch timer control register 0000ABH to AFH 0000B0H Interrupt control register 00 0000B1H Interrupt control register 01 0000B2H Interrupt control register 02 0000B3H Interrupt control register 03 0000B4H Interrupt control register 04 0000B5H Interrupt control register 05 0000B6H Interrupt control register 06 0000B7H Interrupt control register 07 0000B8H Interrupt control register 08 0000B9H Interrupt control register 09 0000BAH Interrupt control register 10 0000BBH Interrupt control register 11 0000BCH Interrupt control register 12 0000BDH Interrupt control register 13
Low-power consumption
(Continued)
22
MB90620A Series
(Continued)
Address Register Register name ICR14 ICR15 Vacancy* Access R/W R/W Resource name Interrupt controller Initial value 00000111 00000111
0000BEH Interrupt control register 14 0000BFH Interrupt control register 15 0000C0H to FFH * : Access prohibited. Explanation of initial values 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. -: This bit is not used. No initial value is defined.
23
MB90620A Series
s INTERRUPT SOURCES AND THEIR INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT9 instruction Exception External interrupt #0 External interrupt #1 External interrupt #2 External interrupt #3 External interrupt #4 External interrupt #5 External interrupt #6 External interrupt #7 Extended serial I/O interface Free-run timer 0 overflow Free-run timer 1 overflow Free-run timer 0 and compare register 0 matched Free-run timer 0 and compare register 1 matched Free-run timer 1 and compare register 0 matched Free-run timer 1 and compare register 1 matched PPG timer #0 PPG timer #1 16-bit reload timer #0 16-bit reload timer #1 16-bit reload timer #2 A/D converter measurement complete Watch prescaler Timebase timer interval interrupt UART 0 transmission complete UART 1 reception complete Delayed interrupt generation module x x x I2OS support x x x #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #33 #35 #36 #37 #39 #42 Interrupt vector No. 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 21H 23H 24H 25H 27H 2AH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF78H FFFF70H FFFF6CH FFFF68H FFFF60H FFFF54H Interrupt control register ICR -- -- -- ICR00 Address -- -- -- 0000B0H
ICR01
0000B1H
ICR02
0000B2H
ICR03 ICR04 ICR05
0000B3H 0000B4H 0000B5H
ICR06
0000B6H
ICR07
0000B7H
ICR08
0000B8H
ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
: The request flag is cleared by the I2OS interrupt clear signal (without stop requests). : The request flag is cleared by the I2OS interrupt clear signal (with stop requests). : The request flag is not cleared by the I2OS interrupt clear signal. Note: Do not set I2OS startup in an ICRXX that does not support I2OS. 24
MB90620A Series
s PERIPHERALS
1. Parallel Ports
The MB90620A series has 59 input/output pins. In the twenty four input/output ports mapped on port 0 to 2, pull-up resistors are selectively added during input state operations depending on the settings in the resistor setting register. P45, P46, port 6 and port 7 are open-drain ports. Port 6 and port 7 are combined with the LCD segment pin function. (1) Register configuration
Port data register Address: PDR1 PDR3 PDR5 PDR7 000001H 000003H 000005H 000007H bit bit 15 14 13 12 11 10 9 8
PDx7
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
PDRx
Port data register Address: PDR0 PDR2 PDR4 PDR6 000000H 000002H 000004H 000006H
7
6
5
4
3
2
1
0
PDx7
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
PDRx
Notes: Bit 7 of port 4 does not have a register bit. Bit 4 to bit 7 of port 5 does not have a register bit.
Port direction register Address: DDR1 DDR3 DDR5 DDR7 000011H 000013H 000015H 000017H bit bit 15 14 13 12 11 10 9 8
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
DDRx
Port direction register Address: DDR0 DDR2 DDR4 DDR6 000010H 000012H 000014H 000016H
7
6
5
4
3
2
1
0
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
DDRx
Notes: Bit 7 of port 4 does not have a register bit. Bit 4 to bit 7 of port 5 does not have a register bit.
Pull-up resistor setting register bit Address: 00001BH RDx7 Pull-up resistor setting register bit Address: 00001AH 00001CH 7 6 5 4 3 2 1 0 RDR0, RDR2 RDx6 RDx5 RDx4 RDx3 RDx2 RDx1 RDx0 RDR1 15 14 13 12 11 10 9 8
RDx7
RDx6
RDx5
RDx4
RDx3
RDx2
RDx1
RDx0
Analog input enable register bit Address: 00001DH -- -- -- -- ADE3 ADE2 ADE1 ADE0 ADER 15 14 13 12 11 10 9 8
25
MB90620A Series
(2) Block Diagram * I/O Port
Internal data bus
Data register read Data register Data register write Direction register Direction register write Pin
Direction register read
* Open-drain Port
Internal data bus
RMW (Read-modify-write instruction) Data register read Data register Data register write Pin
* Port combined with the A/D converter functions
RMW (Read-modify-write instruction)
Internal data bus
Data register read Data register Data register write Direction register Direction register write ADER ADER register write Pin
ADER register read
26
MB90620A Series
* Port with a pull-up resistor option
Pull-up resistor (Approx. 50 k) Data register Port input/output
Bus
Direction register
Resistor register
27
MB90620A Series
2. UART
The UART is a serial I/O port for CLK asynchronous (start-stop synchronization) communications or for CLK synchronous communications. The features of this module are described below: * Full-duplex double buffer * CLK asynchronous (start-stop synchronization) communications and CLK synchronous communications capable * Supports multiprocessor mode * Built-in dedicated baud rate generator CLK asynchronous: 9615, 31250, 4808, 2404, 1202 bps For a 6, 8, 10, 12, or 16 MHz clock. CLK synchronous: 1 M, 500K, 250K, 125K, 62.5K bps Permits setting of any desired baud rate according to an external clock input Error detection function (parity errors, framing errors, and overrun errors) NRZ code as transfer signal Supports Intelligent I/O Service
* * * *
(1) Register Configuration
bit Address: 000020H MD1 MD0 CS2 CS1 CS0 Reserved SCKE SOE 7 6 5 4 3 2 1 0 Serial mode register (SMR)
bit Address: 000021H
15 PEN
14 P
13 SBL
12 CL
11 A/D
10 REC
9 RXE
8 TXE Serial control register (SCR)
bit Address: 000022H
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
0 D0 Serial input register Serial output register (SIDR/SODR)
bit Address: 000023H
15 PE
14 OPE
13 FRE
12 RDRF
11 TDRE
10 --
9 RIE
8 TIE Serial status register (SSR)
bit Address: 000027H
15 MD
14 --
13 --
12 --
11 DIV3
10 DIV2
9 DIV1
8 DIV0 Communication prescaler control register (CDCR)
28
MB90620A Series
(2) Block Diagram
Control signals
Reception interrupt (to CPU)
Dedicated baud rate generator 16-bit timer 0 (internally connected) Transmission clock Clock selection circuit Reception clock
SCK0 Transmission interrupt (to CPU)
External clock Reception control circuit SIN0 Start bit detection circuit Reception bit counter Reception parity counter Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter
SOT0
Reception status determination circuit
Reception shifter
Transmission shifter
Reception error generation signal for I2OS (to CPU)
Reception end
Transmission start
SIDR
SODR
F2MC-16L bus
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
29
MB90620A Series
3. Extended Serial I/O Interface
This block consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSBfirst or MSB-first data transfer can be selected. The serial I/O port to be used can also be selected. The following two serial I/O operation modes are available. Internal shift clock mode: Data transfer is synchronization with the internal clock. External shift clock mode: Data transfer is synchronization with the clock input from the external pin (SCK1). By manipulating the general-purpose port that shares the external pin (SCK1), this mode also enables the data transfer operation to be driven by CPU instructions. (1) Register Configuration
bit Address: 000025H SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT 15 14 13 12 11 10 9 8 Serial mode control status register (SMCS)
bit Address: 000024H
7 --
6 --
5 --
4 --
3 MODE
2 BDS
1 SOE
0 SCOE
bit Address: 000026H
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
0 D0 Serial data register (SDR)
(2) Block Diagram
Internal data bus
(MSB-first) D0 to D7 SIN1 SDR (Serial data register) SOT1
D7 to D0 (LSB-first) Transfer direction selection Read Write
SCK1 Control circuit Shift clock counter
Internal clock
2 SMD2
1 SMD1
0 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
Interrupt request Internal data bus
30
MB90620A Series
4. A/D Converter
The A/D converter converts the analog input voltage into a digital value. The features of this module are as follows: Conversion time: Minimum of 7 s per channel (12 MHz machine clock) RC-type successive approximation conversion method with sample and hold circuit 8-bit/10-bit resolution Analog input is selectable by software from among 4 channels A/D conversion mode selectable from the following three: One-shot conversion mode: Converts a specified channel once. Continuous conversion mode: Converts a specified channel repeatedly. Stop conversion mode: Pauses after converting one channel and wait until the next activation (permits synchronization of start of conversion). * Conversion mode: Single-conversion mode: Converts one channel (when the start and stop channels are the same). Scan conversion mode: Converts several consecutive channels (when the start and stop channels are different). * When A/D conversion is completed, an "A/D conversion complete" interrupt request can be issued to the CPU. Because generating this interrupt can be used to activate the I2OS and transfer the A/D conversion results to memory, this function is suitable for continuous processing. * Activation sources can be selected from among software, an external trigger (falling edge), and timer (rising edge). * * * * * (1) Register Configuration
bit Address: 00002DH
15 BUSY
14 INT
13 INTE
12 PAUS
11 STS1
10 STS0
9
8
STRT Reserved
bit Address: 00002CH
7 MD1
6
5
4
3
2
1
0 ANE0 A/D converter control status register (ADCS1, ADCS0)
MD0 Reserved ANS1
ANS0 Reserved ANE1
bit Address: 00002FH
15 0
14 0
13 0
12 0
11 0
10 0
9 D9
8 D8
bit Address: 00002EH
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
0 D0 A/D converter data register (ADCR1, ADCR0)
31
MB90620A Series
(2) Block Diagram
AV CC
AVRH AVRL AV SS
D/A converter MPX AN0 AN1 AN2 AN3 Sample and hold circuit Data bus Decoder Data register ADCR1, ADCR0 A/D converter control status register 0 A/D converter control status register 1 ATG Reload timer 0 Trigger activation ADCS1, ADCS0 Operating clock Prescaler Sequential comparison register
Input circuit
Comparator
32
MB90620A Series
5. 16-bit Timer (with Event Count Function)
The 16-bit timer consists of a 16-bit down counter, a 16-bit reload register, one input and output pin (TINX,TOTX), and a control register. Three internal clocks and an external clock can be selected for the input clock. When in reload mode, a toggled output waveform is output, while in one-shot mode a square wave indicating that the count is in progress is output pin (TOTX). The input pin (TINX) serves as an event input in event count mode, and can be used for trigger input or gate input in internal clock mode. (1) Register Configuration
bit Address: 000040H : 000046H : 000050H bit Address: 000041H : 000047H : 000051H bit Address: 000042H : 000048H : 000052H bit Address: 000044H : 00004AH : 000054H 15 0 16-bit reload register 0 to 2 (TMRLR0 to TMRLR2) 15 7 6 5 OUTL 4 RELD 3 INTE 2 UF 1 CNTE 0 TRG
MOD0 OUTE
15 --
14 --
13 --
12 --
11 CSL1
10 CSL0
9
8 Timer control status register 0 to 2 (TMCSR0 to TMCSR2) 0 16-bit timer register 0 to 2 (TMR0 to TMR2)
MOD2 MOD1
33
MB90620A Series
(2) Block Diagram
16 16-bit reload register
8
Reload RELD 16-bit down counter UF OUTE OUTL GATE CSL1 Clock selector CSL0 TRG CNTE Clear I2OSCLR Port (Tin) (Tout) OUT CTL. 2 INTE UF IRQ
16 2
F2MC-16L bus
2 IN CTL. EXCK 2
1
Retrigger
2
3
2
5
3 Prescaler clear MOD2 MOD1
Internal clock MOD0
3
34
MB90620A Series
6. 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter, a control status register, and a compare register. * * * * Count clock is selectable from 4 types. A counter over flow interrupt can be generated. An interrupt can be generated on matching with the compare register value. Initialization of the counter on matching with compare register 0 value is enabled depending on the mode settings.
(1) Register Configuration
bit Address: 000056H : 000060H bit 15 T15 14 T14 13 T13 12 T12 11 T11 10 T10 9 T09 8 T08
7 T07
6 T06
5 T05
4 T04
3 T03
2 T02
1 T01
0 T00 Timer data register 0, 1 (TCDT0, TCDT1)
bit Address: 000059H : 000063H bit Address: 000058H : 000062H bit Address: : : : 00005AH 00005CH 000064H 000066H
15 ICP1
14 ICP0
13 ICE1
12 ICE0
11 --
10 --
9 CST1
8 CST0 Compare control status 0, 1 register (CCS0, CCS1)
7
Reserved
6 IVF
5 IVFE
4 STOP
3 MODE
2 CLR
1 CLK1
0 CLK0 Timer control status 0, 1 register (TCS0, TCS1)
15 C15
14 C14
13 C13
12 C12
11 C11
10 C10
9 C09
8 C08
bit
7 C07
6 C06
5 C05
4 C04
3 C03
2 C02
1 C01
0 C00 Timer 0, 1 compare register (TCR00, TCR01/ TCR10, TCR11)
35
MB90620A Series
(2) Block Diagram
Interrupt request
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Divider
Comparator 0 Bus
16-bit up-counter T00 to T15
Clock
Compare register X0 T00 to T15 Compare register X1
Compare match interrupt
Compare match interrupt
36
MB90620A Series
7. 16-bit PPG Timer
This module can output a pulse synchronized with an external trigger or a software trigger. In addition, the cycle and duty ratio of the output pulse can be changed as desired by overwriting the two 16-bit register values. Synchronizes pulse with trigger, and permits programming of the pulse output by overwriting the register values mentioned above. This function permits use as a D/A converter with the addition of external circuits. One-shot function: Detects the edge of trigger input, and permits single-pulse output. (1) Register Configuration PWM function:
bit Address: 00035H : 0003DH bit Address: 00034H : 0003CH bit Address: 00031H : 00039H bit Address: 00030H : 00038H bit Address: 00033H : 0003BH bit Address: 00032H : 0003AH
15
14
13
12
11 CKS1
10 CKS0
9 PGMS
8 -- PPG0, 1 control status register (PCNH0, PCNH1)
CNTE STGR MDSE RTRG
7 EGS1
6 EGS0
5 IREN
4 IRQF
3 IRS1
2 IRS0
1 POEN
0 OSEL PPG0, 1 control status register (PCNL0, PCNL1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 PPG0, 1 cycle setting register (PCSR0, PCSR1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 PPG0, 1 duty setting register (PDUT0, PDUT1)
37
MB90620A Series
(2) Block Diagram
PCSR
PDUT
Prescaler /2 /8 /32 /128 16-bit down-counter ck Load
cmp
Start
Borrow
PPG mask
S
Q
PPG output
R
Reverse bit
Enable Interrupt selector IRQ
TRG input
Edge ditection
Software trigger
38
MB90620A Series
8. LCD Controller/driver
The LCD controller driver consists of the display controller for generating the segment signal and common signal according to data set in the display data memory, the segment driver and the common driver capable of directly driving the LCD panel (Liquid Crystal Display). Primary functions are as follows; * * * * * * LCD direct drive function Common output 4 channels (COM0 to COM3), segment output 32 channels (SEG0 to SEG31) Built-in 16 bytes of data memory for display Duty ratio selective from 1/2, 1/3 and 1/4 Driving clock source selective from the main clock (4 MHz) and the sub clock (32 kHz) SEG 16 to SEG 31 can be used as open-drain ports.
(1) Register Configuration
LCD control register bit Address: 000080H : 000081H LCD display RAM Address: 000080H b3 b7 b3 Address: 000080H b7 b3 Address: 000080H
: :
15 LCR1
87 LCR0
0 LCR0/LCR1
b2 b6 b2 b6 b2 b6
: :
b1 b5 b1 b5 b1 b5
: :
b0 b4 b0 b4 b0 b4
: :
SEG00 SEG01 SEG02 SEG03 SEG04 SEG05
b7
: :
b3 Address: 000080H b7 b3 Address: 000080H b7
: :
b2 b6 b2 b6
:
b1 b5 b1 b5
:
b0 b4 b0 b4
:
SEG16 SEG17 SEG18 SEG19
b3 Address: 000080H b7 b3 b7 COM3
b2 b6 b2 b6 COM2
b1 b5 b1 b5 COM1
b0 b4 b0 b4 COM0
SEG28 SEG29 SEG30 SEG31
Address: 000080H
39
MB90620A Series
(2) Block Diagram
4 MHz 32 kHz LCDC control register LCR
Power supply input (V0 to V3)
Common driver
4 Prescaler Timing controller
COM0 COM1 COM2 COM3
Internal bus
AC converter
Segment driver
32 LCD display RAM (16 bytes)
SEG00 SEG01 SEG02 SEG03 SEG04
* * * * * * * *
SEG27 SEG28 SEG29 SEG30 SEG31
Controller
Driver
40
MB90620A Series
9. DTP/External Interrupt
The DTP (Data Transfer Peripheral) is a peripheral, positioned between peripherals external to the device and the F2MC-16L CPU, that accepts DMA requests or interrupt requests generated by external peripherals and transfers them to the F2MC-16L CPU to activate the Intelligent I/O Service or interrupt processing. In the case of the Intelligent I/O Service, there are two request levels that can be selected: high and low; in the case of an external interrupt request, there are a total of four request levels that can be selected: high, low, rising edge and falling edge. (1) Register Configuration
bit Address: 000029H : 000028H bit Address: 00002BH : 00002AH 15 ELVR 15 EIRR ENIR 0 Request level setting register 0 DTP/Interrupt enable register
(2) Block Diagram
4 DTP/Interrupt enable register 3
F2MC-16L bus
4
Gate
Source F/F
Edge detector
Request input
4
DTP/Interrupt source register
8
Request level setting register
10. Watchdog Timer, Timebase Timer, and Watch Timer Functions
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller. The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the timebase timer uses the main clock, regardless of the setting of the MCS bit and SCS bit in CKSCR. The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the watch timer uses the sub clock, regardless of the setting of the MCS bit and SCS bit in CKSCR. (1) Register Configuration
bit Address: 0000A8H 7 PONR 6 -- 5 WRST 4 ERST 3 SRST 2 WTE 1 WT1 0 WT0 Watchdog timer control register (WDTC)
bit Address: 0000A9H
15 Reserved
14 --
13 --
12 TBIE
11 TBOF
10 TBR
9 TBC1
8 TBC0 Timebase timer control register (TBTC)
bit Address: 0000AAH
7 WDCS
6 SCE
5 WTIE
4 WTOF
3 WTR
2 WTC2
1
0 Watch timer control register (WTC)
WTC1 WTC0
41
MB90620A Series
(2) Block Diagram
Main clock TBTC TBC1 TBC0 TBR TBIE F2MC-16L bus TBOF Timebase interrupt WDTC WT1 Selector WT0 WTE 2-bit counter OF CLR Watchdog reset generator CLR WDGRST To internal reset generator AND Q S R Selector 212 214 216 219 TBTRES Clock input Timebase timer 212 214 216 219
WTC AND WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF Timer interrupt AND Q S R S QR Selector SCM Power-on reset sub clock stops 29 210 213 214 215 210 11 2 Watch timer 212 213 14 2 Clock input 215 WTRES Sub clock
WDTC PONR WRST ERST SRST RST pin From RST bit in the STBYC register From power-on generation
42
MB90620A Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module generates task switching interrupts. This module can be used to generate/cancel interrupt requests to the F2MC-16L CPU by software. (1) Register Configuration
bit Address: 00009FH 15 -- 14 -- 13 -- 12 -- 11 -- 10 -- 9 -- 8 R0 Delayed interrupt source generation/release register (DIRR)
(2) Block Diagram
F2MC-16L bus
Delayed interrupt source generation/release decoder
Source latch
Delayed interrupt generation module Other requests
Interrupt controller
WRITE
F2MC-16L CPU
ICR yy CMP DDIR ICR xx
IL CMP ILM INTA
43
MB90620A Series
12. Low-power Consumption Controller (CPU Intermittent Operation Function, Oscillation Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, Pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the PLL clock mode, all of the other operating modes are low-power consumption modes. In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is stopped. In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as the operation clock, and the main clock and PLL clock are stopped. In PLL sleep mode and main sleep mode, only the CPU's operation clock is stopped; all clocks other than the CPU clock operate. In Pseudo-watch mode, only the watch timer and timebase timer operate. In PLL watch mode, main watch mode, and sub watch mode, only the watch timer operates. In this mode, only the sub clock is used for operation, while the main clock and the PLL clock are stopped (the difference between the PLL watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt in the PLL clock mode, the main clock modes and the sub clock mode respectively, and there is no difference in the watch mode). The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain data while consuming the least amount of power. (The difference between the main stop mode and the sub stop mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no difference in the stop mode.) The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power consumption by reducing the execution speed of the CPU while supplying a hig-speed clock and using on-chip resources. The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks are divided by 2 to be used as a machine clock. The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode and hardware standby mode are woken up. (1) Register Configuration
bit Address: 0000A0H 7 STP 6 SLP 5 SPL 4 RST 3 TMD 2 CG1 1 CG0 0 SSR Low-power consumption mode control register (LPMCR)
bit Address: 0000A1H
15 SCM
14 MCM
13 WS1
12 WS0
11 SCS
10 MCS
9 CS1
8 CS0 Clock selection register (CKSCR)
44
MB90620A Series
(2) Block Diagram
CKSCR SCM SCS Sub clock switching control Sub clock (OSC oscillation)
CKSCR MCM MCS CKSCR CS1 CS0 CPU Clock selector 1/2 S PLL multiplier circuit 1 2 3 4 CPU system clock generation Main clock (OSC oscillation) CPU clock
0/9/17/33 intermittent cycle selection
F2MC-16L bus
LPMCR CG1 CG0 CPU intermittent operation function Cycle count selection circuit Peripheral clock generation SCM SLEEP Standby controller RST cancel MSTP STOP Main OSC stop Sub OSC stop Peripheral clock
LPMCR SLP STP TMD
Interrupt request or RST CKSCR WS1 WS0 LPMCR SPL Pin high-impedance controller Oscillation stabilization delay time selector 24 213 215 218 Clock input Timebase timer 212 214 216 219 Pin HI-Z
SSR
Self-refresh control circuit
Self-refresh
LPMCR RST
Internal reset generator
RST pin Internal RST To watchdog timer WDGRST
45
MB90620A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage AVCC*
1 1
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -40 -55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VCC + 0.3 15 50 -4 -48 +400 +85 +150
Unit V V V V V mA mA mA mA mW C C
Remarks
AVRH* AVRL Input voltage*2 Output voltage*
2
VI VO IOL IOL IOH IOH Pd TA TSTG
"L" level output current "L" level total output current "H" level output current "H" level total output current Power consumption Operating temperature Storage temperature
*1: AVCC, AVRH and AVRL must not exceed VCC. In addition, AVRL must not exceed AVRH. *2: VI or VO must not exceed VCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Power supply voltage "H" level input voltage "L" level input voltage Operating temperature Symbol VCC VIH VIHS VIL VILS TA Value Min. 4.0 2.7 0.7 VCC 0.8 VCC VSS - 0.3 VSS - 0.3 -40 Max. 5.5 5.5 VSS + 0.3 VSS + 0.3 0.8 0.2 VCC +85 Unit V V V V V V C Remarks Normal operation Maintaining the stop status Except VIHS Hysteresis inputs Except VILS Hysteresis inputs
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 46
MB90620A Series
3. DC Characteristics
(VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter "H" level output voltage "L" level output voltage Input leakage current Pull-up resistor Symbol VOH VOL IIL R ICC ICC ICC Power supply current ICCS VCC ICCL ICCT ICCH LCD voltage division resistor COM0 to COM3 output impedance SEG 0 to SEG31 output impedance LCD leakage current Input capacitance Open-drain output leakage current RLCD RVCOM RVSEG ILCDL CIN Ileak -- -- -- --
Except VCC, VSS Opendrain pin
Pin name -- -- -- --
Condition VCC = 4.5 V IOH = -4.0 mA VCC = 4.5 V IOH = -4.0 mA VCC = 5.5 V Value Min. VCC - 0.5 -- -10 22 -- -- -- -- Typ. -- -- -- -- 40 30 15 10 6 50 1 500 -- -- -- 10 0.1 Max. -- 0.4 10 110 80 60 40 40 10 200 10 750 2.5 15 10 -- 10
Unit V V A k
Remarks
mA In 12 MHz operation mA In 8 MHz operation mA In 4 MHz operation mA In 12 MHz sleep mA A A k k k A pF A In 32 KHz sub operation In 32 KHz watch mode In stop mode
-- -- -- -- Between VCC and V0, VCC = 5.0 V V1 - V3 = 5.0 V V1 - V3 = 5.0 V -- -- -- 300 -- -- -10 -- --
47
MB90620A Series
4. AC Characteristics
(1) Clock Timing * When VCC = 4.0 V to 5.5 V (VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Source oscillation frequency Source oscillation cycle time Frequency fluctuation ratio*1 (when locked) Input clock pulse width Input clock rising/falling time Internal operating clock frequency Internal operating clock cycle time Symbol FC tC f PWH, PWL tcr, tcf fCP tCP Pin name X0, X1 X0, X1 -- X0 X0 -- -- Condition -- -- -- -- -- -- -- Value Min. 3 41.66 -- 12 -- 32 K*2 83.5 Max. 24 333 3 -- 5 12 M 31250 Unit MHz ns % ns ns Hz ns Use duty ratio of 30 to 70% as a guide Remarks
*1: The frequency fluctuation ratio indicates the maximum fluctuation ratio from the set center frequency while locked with multiply.
f =
f0
+
x 100 (%)
Center frequency f 0 -
*2: 32 KHz operation means sub operation. * Relationship between Operating Clock Frequency and Power Supply Voltage
V CC [V] 5.5
4.0
f CP [Hz] 32 K 12 M
48
MB90620A Series
* Clock Timing
tC 0.8 V CC 0.2 V CC P WH t cf P WL t cr
* PLL Operation Assurance Range
Relationship between internal operation clock frequency and power supply voltage
Power supply V CC (V)
5.5 Normal operation range 4.0 2.7 f CP (MHz) : PLL operation assurance range PLL operation assurance range
1.5
3 Internal clock
8
12
: Operation assurance range
Relationship between source oscillation frequency, internal operating clock frequency
Multiply by 3 Multiply by 2 Internal clock f CP (MHz) 12
Multiply by 1
No multiplier
8
4
0
34
8
12
16
24
FC (MHz)
Source oscillation clock FC (MHz)
49
MB90620A Series
(2) Reset Input Timing (VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Reset input time Pin Symbol name tRSTL RST Condition -- Value Min. 4 tC Max. -- Unit ns Remarks
t RSTL
RST
0.2Vcc 0.2Vcc
(3) Power-on Reset (VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Pin name Condition VCC VCC -- -- Value Min. -- 1 Max. 30 -- Unit ms ms Remarks
tR 2.25 V
V CC
0.2 V
If power supply voltage needs to be changed in the course of operation, a smooth voltage rise is recommended by suppressing the voltage variation as shown below. Also, do not use the PLL clock when varying the voltage. However, the supply voltage can be changed when using the PLL clock if the voltage drops by less than 1 mV/s.
5.0 V
V CC
2.7 V Hoding RAM data V SS
It is recommended that the rate of increase in the voltage be kept to no more than 50 mV/ms.
50
MB90620A Series
(4) UART Timing (VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time SCK0 SOT0 delay time Valid SIN0 SCK0 SCK0 Valid SIN0 hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK0 SOT0 delay time Valid SIN0 SCK0 SCK0 Valid SIN0 hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name -- -- -- -- -- -- -- -- -- For external shift clock mode output pin, CL = 80 pF+1 TTL Condition Value Min. 8 tCP -80 100 60 4 tCP 4 tCP -- 60 60 Max. -- 80 -- -- -- -- 150 -- -- Unit ns ns ns ns ns ns ns ns ns Remarks
For internal shift clock mode output pin, CL = 80 pF+1 TTL
Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance added to pins during testing. * tCP is the internal operating clock cycle time (unit: ns). * The values in the table are target values.
51
MB90620A Series
* Internal Shift Clock Mode
t SCYC
SCK0
2.4 V 0.8 V t SLOV 0.8 V
SOT0
2.4 V 0.8 V t IVSH 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC
SIN0
* External Shift Clock Mode
t SLSH
t SHSL 0.8 V CC 0.8 V CC
SCK0
0.2 V CC t SLOV
0.2 V CC
SOT0
2.4 V 0.8 V t IVSH 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC
SIN0
52
MB90620A Series
(5) Extended Serial I/O Timing (VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time SCK1 SOT1 delay time Valid SIN1 SCK1 Serial clock "H" pulse width Serial clock "L" pulse width SCK1 SOT1 delay time Valid SIN1 SCK1 Pin Symbol name tSCYC tSLOV tIVSH tSHSL tSLSH tSLOV tIVSH -- -- -- -- -- -- -- -- -- Condition -- VCC = 5.0 V 10% -- -- VCC = 5.0 V 10% VCC = 5.0 V 10% -- -- -- Value Min. 8 tXMCYL -- 1 tXMCYL 1 tXMCYL 230 230 2 tXMCYL 1 tXMCYL 1 tXMCYL Max. -- 80 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns For external shift clock mode output pin, CL = 80 pF Max. 2 MHz Remarks
SCK1 Valid SIN1 hold time tSHIX
For internal shift clock mode output pin, CL = 80 pF+1 TTL
SCK1 Valid SIN1 hold time tSHIX
Notes: * CL is the load capacitance added to pins during testing. * tXMCYL is the internal operation clock cycle time (unit: ns). * Internal Shift Clock Mode
t SCYC
SCK1
2.4 V 0.8 V t SLOV 0.8 V
SOT1
2.4 V 0.8 V t IVSH 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC
SIN1
* External Shift Clock Mode
t SLSH t SHSL 0.8 V CC 0.2 V CC t SLOV 0.2 V CC 0.8 V CC
SCK1
SOT1
2.4 V 0.8 V t IVSH 0.8 V CC 0.2 V CC t SHIX 0.8 V CC 0.2 V CC
SIN1
53
MB90620A Series
(6) Timer Input Timing (VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIO0 to TIO2 Condition -- Value Min. 4 tCP Max. -- Unit ns Remarks
0.8 V CC
0.8 V CC 0.2 V CC 0.2 V CC
t TIWH
t TIWL
(7) Trigger Input Timing (VCC = 4.0 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Trigger input width Symbol tTRWH tTRWL Pin name ADT TRG Condition -- Value Min. 4 tCP Max. -- Unit ns Remarks A/D trigger
0.8 V CC
0.8 V CC 0.2 V CC 0.2 V CC
t TRWH
t TRWL
54
MB90620A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +2.7 V to 5.5 V, AVSS = VSS = 0.0 V, +2.7 V AVRH - AVRL, TA = -40C to +85C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Interchannel disparity Symbol -- -- -- -- VOT VFST -- IAIN VAIN -- -- IA IAH IR IRH -- Pin name -- -- -- -- AN0 to AN3 AN0 to AN3 -- AN0 to AN3 AN0 to AN3 AVRH AVRL AVCC AVCC AVCC AVCC AN0 to AN3 Value Min. -- -- -- -- -1.5 AVRH - 3.5 8.16 -- AVRL AVRL -- -- -- -- -- -- Typ. 10 -- -- -- +0.5 AVRL - 1.5 -- -- -- -- -- 5 -- 200 -- -- Max. 10 3.0 1.5 1.5 +2.5 AVRH + 0.5 -- 10 AVRH AVCC AVRH -- 5* -- 5* 4 Unit bit LSB LSB LSB LSB LSB s A V V V mA A A A LSB
* : Current when the A/D converter is not operating and the CPU is stopped (when VCC = AVCC = AVRH = +5.5 V) Notes: * The smaller | AVRH - AVRL |, the greater the error would become relatively. * The output impedance of the external circuit for the analog input must satisfy the following conditions: The output impedance of the external circuit should be less than approximately 7 k. * If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 5 s @ at a machine clock of 12 MHz). * Analog Input Circuit Model Diagram
Analog input R ON0 R ON1 C1
C0 Comparator
R ON0 = Approx. 1.5 k (5.0 V) R ON1 = Approx. 1.0 k (5.0 V) C 0 = Approx. 60 pF (5.0 V) C 1 = Approx. 4 pF (5.0 V)
Note: Use the values shown as guides only.
55
MB90620A Series
6. A/D Converter Glossary
* Resolution Analog changes that are identifiable with the A/D converter. If the resolution is 10 bits, the analog voltage can be resolved into 210 = 1024 steps. * Total error The deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and noise. * Linearity error The deviation between the actual conversion characteristic of the device and the line linking the zero transition point ("00 0000 0000" "00 0000 0001") and the full scale transition point ("11 1111 1110" "11 1111 1111"). * Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
Digital output 11 1111 1111 11 1111 1110
* * * * * * * * * * *
(1 LSB x N + V OT)
Linearity error
00 0000 0010 00 0000 0001 00 0000 0000 V OT V FST - V OT 1022 V NT - (1 LSB x N + V OT ) 1 LSB [LSB] V NT V (N+1)T
Analog input V FST
1 LSB =
Linearity error =
Differential linearity error =
V(N + 1)T - V NT - 1 [LSB] 1 LSB
56
MB90620A Series
s EXAMPLE CHARACTERISTICS
Power supply current vs temperature characteristics example MB90623A/622A Current consumption characteristics example
PLL Stop External oscillator: 8 MHz (Internal 4 MHz) Power supply voltage: 5.0 V
60 50
Current value (mA)
40 30 20 10 0 -40
25 Temperature (C)
85
Power supply current vs temperature characteristics example MB90623A/622A Current consumption characteristics example
60 50
Current value (mA)
PLL Stop External oscillator: 16 MHz (Internal 8 MHz) Power supply voltage: 5.0 V
40 30 20 10 0 -40 25 Temperature (C) 85
Power supply current vs temperature characteristics example MB90623A/622A Current consumption characteristics example
PLL Stop External oscillator: 24 MHz (Internal 12 MHz) Power supply voltage: 5.0 V
60 50
Current value (mA)
40 30 20 10 0 -40 25 Temperature (C) 85
(Continued)
57
MB90620A Series
Operation frequency vs power supply current characteristics example MB90623A/622A Current consumption characteristics example
60 50
Current value (mA)
PLL Stop External oscillator/2 = Internal frequency Power supply voltage: 5.0 V Temperature: 25C
40 30 20 10 0 4 8 Internal frequency (MHz) 12
Sleep mode power supply current characteristics example Sleep mode current consumption characteristics example
8 7
Current value (mA)
External oscillator: 4 MHz Temperature: 25C
6 5 4 3 2 1 0 4.0 4.5 5.0 5.5 Power supply voltage (V)
Power supply voltage vs power supply current characteristics example Power supply voltage vs power supply current characteristics example
60 Temperature: 25C
Power supply current (mA)
50 40 30 20 EXT 8 MHz (Internal 4 MHz) 10 0 4.0 4.5 5.0 5.5 EXT24 MHz (Internal 12 MHz) EXT20 MHz (Internal 10 MHz) EXT16 MHz (Internal 8 MHz)
Power supply voltage (V)
(Continued)
58
MB90620A Series
Sub operation mode power supply current characteristics example Sub operation mode current consumption characteristics example
10 9 8
Current value (mA)
Operation frequency: 32 KHz Temperature: 25C
7 6 5 4 3 2 1 0 4.0 4.5 5.0 5.5
Power supply voltage (V)
Watch mode power supply current characteristics example Watch mode current consumption characteristics example
16 14
Current value (mA)
Operation frequency: 32 KHz Temperature: 25C
12 10 8 6 4 2 0 4.0 4.5 5.0 5.5 Power supply voltage (V)
Power supply current characteristics during PLL operation Power supply current characteristics during PLL operation
60
Power supply current (mA)
50 40 30 20 10 0 4.0
Oscillation frequency: 4 MHz Temperature: 25C
Multiply by 3 (Internal 12 MHz) Multiply by 2 (Internal 8 MHz) Multiply by 1 (Internal 4 MHz)
4.5
5.0
5.5
Power supply voltage (V)
(Continued)
59
MB90620A Series
(Continued)
Pseudo-watch mode power supply current characteristics example Pseudo-watch mode current consumption characteristics example
2.00 1.80 1.60
Current value (mA)
Oscillation frequency: main 4 MHz sub 32 KHz Temperature: 25C
1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 4.0 4.5 5.0 5.5 Power supply voltage (V)
CPU intermittent mode power supply current characteristics CPU intermittent mode power supply current characteristics
30
Power supply current (mA)
25 20 15
Power supply voltage: 5.0 V Temperature: 25C
10 5 0 None Interval (1/3) Interval (1/6)
Oscillation 6 MHz Oscillation 4 MHz Oscillation 2 MHz
Interval (1/9)
Power supply voltage (V)
60
MB90620A Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
I S T N Z V C RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
61
MB90620A Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL:AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b
62
MB90620A Series
(Continued)
Symbol rel ear eam rlst Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension * Meaning
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note: The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
63
MB90620A Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing Listed in tables of instructions 1 2 1 1 2 2 0 0
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Note: "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand (c) word (d) long
Number Number Number Number Number Number of of of of cycles access of cycles access of cycles access +0 +0 +0 +1 +1 +1 1 1 1 1 1 1 +0 +0 +2 +1 +4 +4 1 1 2 1 2 2 +0 +0 +4 +2 +8 +8 2 2 4 2 4 4
Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits)
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
64
MB90620A Series
Table 7 Mnemonic
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam
Transfer Instructions (Byte) [41 Instructions] R G
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
#
2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+
~
3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a)
B
(b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b)
Operation
byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LA HH
Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X - - - - - - - - - - - - - - - - - Z Z - - * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S T N Z V C RM W
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
65
MB90620A Series
Table 8 Mnemonic
MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 dir, A addr16, A SP, A RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16
Transfer Instructions (Word/Long Word) [38 Instructions] ~
3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 4 5+ (a) 3 4 5+ (a)
#
2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+
R G
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0
B
(c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2x (c) 0 2x (c) 0 (d) 0 0 (d)
Operation
word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A)
LA HH
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S T N Z V C RM W
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW AL, AH /MOVW @A, T XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A, ear A, eam RWi, ear RWi, eam A, ear A, eam A, #imm32 ear, A eam, A
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
66
MB90620A Series
Table 9 Mnemonic
ADD A,#imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB A, #imm8 SUB A, dir SUB A, ear SUB A, eam SUB ear, A SUB eam, A SUBC A SUBC A, ear SUBC A, eam SUBDC A ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam A, ear A, eam A, #imm32 A, ear A, eam A, #imm32
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] #
2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5
~
2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 6 7+ (a) 4 6 7+ (a) 4
R G
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
B
0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0
Operation
byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (decimal) byte (A) (A) -imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (decimal) word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32
LA HH
Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S T N Z V C RM W
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
67
MB90620A Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ R G B Operation LA HH - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - S - - - - - - - - - - - - T - - - - - - - - - - - - N * * * * * * * * * * * * Z * * * * * * * * * * * * V * * * * * * * * * * * * C RM W - - - - - - - - - - - - - * - * - * - * - * - *
2 2 2 0 byte (ear) (ear) +1 2+ 5+ (a) 0 2x (b) byte (eam) (eam) +1 2 3 2 0 byte (ear) (ear) -1 2+ 5+ (a) 0 2x (b) byte (eam) (eam) -1 2 3 2 0 word (ear) (ear) +1 2+ 5+ (a) 0 2x (c) word (eam) (eam) +1 2 3 2 0 word (ear) (ear) -1 2+ 5+ (a) 0 2x (c) word (eam) (eam) -1 2 7 4 0 long (ear) (ear) +1 2+ 9+ (a) 0 2x (d) long (eam) (eam) +1 2 7 4 0 long (ear) (ear) -1 2+ 9+ (a) 0 2x (d) long (eam) (eam) -1
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ R G 0 1 0 0 0 1 0 0 B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32 LA HH - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V * * * * * * * * * * * C RM W * * * * * * * * * * * - - - - - - - - - - -
1 1 2 2 2+ 3+ (a) 2 2 1 1 2 2 2+ 3+ (a) 3 2
2 6 2 2+ 7+ (a) 0 5 3 0
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
68
MB90620A Series
Table 12 Mnemonic
DIVU DIVU DIVU DIVUW DIVUW MULU MULU MULU MULUW MULUW MULUW A A, ear
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] #
1 2
~
*1 * * *
2 3 4
R G
0 1 0 1 0 0 1 0 0 1 0
B
0 0 *
6
Operation
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) long (A)/word (ear) Quotient word (A) Remainder word (ear) long (A)/word (eam) Quotient word (A) Remainder word (eam)
LA HH
- - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - -
S
- - - - - - - - - - -
T
- - - - - - - - - - -
N
- - - - - - - - - - -
Z
- - - - - - - - - - -
V
* * * * * - - - - - -
C RM W
* * * * * - - - - - - - - - - - - - - - - -
A, eam 2+ A, ear 2
0 *
7
A, eam 2+ A 1 A, ear 2 A, eam 2+ A 1 A, ear 2 A, eam 2+
*5 *8 *9 *10 *11 *12 *13
0 byte (AH) *byte (AL) word (A) 0 byte (A) *byte (ear) word (A) (b) byte (A) *byte (eam) word (A) 0 word (AH) *word (AL) long (A) 0 word (A) *word (ear) long (A) (c) word (A) *word (eam) long (A)
*1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
69
MB90620A Series
Table 13 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions] R G B Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a)
0 0 1 0 0 (b) 2 0 0 2x (b) 0 0 1 0 0 (b) 2 0 0 2x (b) 0 0 1 0 0 (b) 2 0 0 2x (b)
1 2 0 0 byte (A) not (A) 2 3 2 0 byte (ear) not (ear) 2+ 5+ (a) 0 2x (b) byte (eam) not (eam) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) 0 0 0 0 1 0 0 (c) 2 0 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
1 2 0 0 word (A) not (A) 2 3 2 0 word (ear) not (ear) 2+ 5+ (a) 0 2x (c) word (eam) not (eam)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
70
MB90620A Series
Table 14 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # ~ Logical 2 Instructions (Long Word) [6 Instructions] R G B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LA HH - - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V R R R R R R C RM W - - - - - - - - - - - -
2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0
XORL A, ea XORL A, eam
Table 15 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions] R G 0 B 0 Operation byte (A) 0 - (A) LA HH X - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V * * * * * * C RM W * * * * * * - - * - - *
2 3 2 0 byte (ear) 0 - (ear) 2+ 5+ (a) 0 2x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2 0 word (ear) 0 - (ear) 2+ 5+ (a) 0 2x (c) word (eam) 0 - (eam)
Table 16 Mnemonic NRML A, R0 # 2 ~ *1 RG 1
Normalize Instruction (Long Word) [1 Instruction] B 0 is "1" Operation
long (A) Shift
LA HH - -
I -
S -
T -
N -
Z *
V -
C RM W - -
until first digit shift count
byte (R0) Current
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
71
MB90620A Series
Table 17 Mnemonic
RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ear eam ear eam A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions] B
0 0 0 2x (b) 0 2x (b) 0 0 0 0 0 0 0 0 0 0 0 0
#
2 2
~
2 2
R G
0 0 2 0 2 0 1 1 1 0 0 0 1 1 1 1 1 1
Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Arithmetic right shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
LA HH
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - -
S T N Z V C RM W
- - - - - - - - - - - - - - - - - - - - - - - - * * - * * - * * - * * - * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * - - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL LSRL LSLL A, R0 A, R0 A, R0
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
72
MB90620A Series
Table 18 Mnemonic
BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP CALLP CALLP rel rel rel rel
Branch 1 Instructions [31 Instructions] B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0
#
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4
~
*1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
Operation
Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15 (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15 (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23
LA HH
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S T N Z V C RM W
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 @eam *6 addr24 *7
(c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c)
*1: *2: *3: *4: *5: *6: *7:
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
73
MB90620A Series
Table 19 Mnemonic
CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE CWBNE CWBNE DBNZ DBNZ DWBNZ DWBNZ INT INT INTP INT9 RETI LINK ear, #imm8, rel eam, #imm8, rel*9 ear, #imm16, rel eam, #imm16, rel*9 ear, rel eam, rel ear, rel eam, rel #vct8 addr16 addr24
Branch 2 Instructions [19 Instructions] B
0 0 0 (b) 0 (c) 0
#
3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2
~ RG
*1 *1 *2 *3 *4 *3 *5 *6 *5 *6 20 16 17 20 15 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0
Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LA HH
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - R R R R * -
S
- - - - - - - - - - S S S S * -
T
- - - - - - - - - - - - - - * -
N
* * * * * * * * * * - - - - * -
Z
* * * * * * * * * * - - - - * -
V
* * * * * * * * * * - - - - * -
C RM W
* * * * * * - - - - - - - - * - - - - - - - - * - * - - - - - -
Branch when byte (ear) = (ear) - 1, and (ear) 0 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) 6x (c) (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
#local8
UNLINK RET *7 RETP *8
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
*1: *2: *3: *4: *5: *6: *7: *8: *9:
5 when branching, 4 when not branching 13 when branching, 12 when not branching 7 + (a) when branching, 6 + (a) when not branching 8 when branching, 7 when not branching 7 when branching, 6 when not branching 8 + (a) when branching, 7 + (a) when not branching Retrieve (word) from stack Retrieve (long word) from stack In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
74
MB90620A Series
Table 20 Mnemonic
PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR A AH PS rlst A AH PS rlst @A CCR, #imm8 CCR, #imm8
Other Control Instructions (Byte/Word/Long Word) [28 Instructions] ~
4 4 4 *3 3 3 4 *2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 *1 1 1 1 1 1 1 1 1
#
1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1
RG
0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
B
(c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LA HH
- - - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - -
I
- - - - - - * - * * * - - - - - - - - - - - - - - - - -
S T N Z V C RM W
- - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte (CCR) (CCR) and imm8 byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank
MOV RP, #imm8 MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
75
MB90620A Series
Table 21 Mnemonic
MOVB MOVB MOVB MOVB MOVB MOVB SETB SETB SETB CLRB CLRB CLRB BBC BBC BBC BBS BBS BBS SBBS WBTS WBTC A, dir:bp A, addr16:bp A, io:bp dir:bp, A addr16:bp, A io:bp, A dir:bp addr16:bp io:bp dir:bp addr16:bp io:bp dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel addr16:bp, rel io:bp io:bp
Bit Manipulation Instructions [21 Instructions] B
(b) (b) (b)
#
3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3
~
5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Operation
byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LA HH
Z Z Z - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - -
S T N Z V C RM W
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
2x (b) Branch when (addr16:bp) b = 1, bit = 1 * *
5 5
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
*1: *2: *3: *4: *5:
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
76
MB90620A Series
Table 22 Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 R G 0 0 0 0 0 0 B 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension LA HH - - X - Z - - * - X - Z I - - - - - - S - - - - - - T - - - - - - N - - * * R R Z - - * * * * V - - - - - - C RM W - - - - - - - - - - - -
Table 23 Mnemonic
MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI MOVSW/MOVSWI MOVSWD SCWEQ/SCWEQI SCWEQD FILSW/FILSWI
String Instructions [10 Instructions] Operation LA HH
- - - - - - - - - - - - - - - - - - - -
#
2 2 2 2 2 2 2 2 2 2
~
*2 *2 *1 *1 6m +6 *2 *2 *1 *1 6m +6
R GB
*5 *5 *5 *5 *5 *8 *8 *8 *8 *8
I
- - - - - - - - - -
S
- - - - - - - - - -
T
- - - - - - - - - -
N
- - * * * - - * * *
Z
- - * * * - - * * *
V
- - * * - - - * * -
C RM W
- - * * - - - * * - - - - - - - - - - -
*3 Byte transfer @AH+ @AL+, counter = RW0 *3 Byte transfer @AH- @AL-, counter = RW0 *4 Byte retrieval (@AH+) - AL, counter = RW0 *4 Byte retrieval (@AH-) - AL, counter = RW0 *3 Byte filling @AH+ AL, counter = RW0 *6 Word transfer @AH+ @AL+, counter = RW0 *6 Word transfer @AH- @AL-, counter = RW0 *7 Word retrieval (@AH+) - AL, counter = RW0 *7 Word retrieval (@AH-) - AL, counter = RW0 *6 Word filling @AH+ AL, counter = RW0
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
77
MB90620A Series
s ORDERING INFORMATION
Model MB90622PFV MB90623PFV MB90P623PFV Package 100-pin Plastic LQFP (FPT-100P-M05) Remarks
78
MB90620A Series
s PACKAGE DIMENSIONS
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
14.000.10(.551.004)SQ
51
1.50 -0.10 +.008 .059 -.004
+0.20
(Mounting height)
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05
"A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001
+0.08
0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimension in mm (inches)
79
MB90620A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9704 (c) FUJITSU LIMITED Printed in Japan
80

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